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T6C13B 2001-02-05 1/11 toshiba cmos digital integrated circuit silicon monolithic T6C13B column and row driver for a dot matrix lcd the T6C13B is a 240 ? channel ? output column and row driver for an stn dot matrix lcd. the T6C13B features a 42 ? v lcd drive voltage and a 20 ? mhz maximum operating frequency. the T6C13B is able to drive lcd panels with a duty ratio of up to 1 / 480. features display duty application : to 1 / 480 lcd drive signal : 240 data transfer : 8 ? bit bidirectional operating frequency : 27 mhz (v dd = 4.5 to 5.5 v) lcd drive voltage : 14 to 40 v power supply voltage : 2.7 to 5.5 v operating temperature : ? 20 to 75c lcd drive output resistance : 800 ? (max) (20 v, 1 / 13 bias) display ? off function : when / dspof is l, all lcd drive outputs (o1 to o240) remain at the v 5 level. low power consumption : cascade connection and auto enable transfer functions are available. toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in g eneral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury o r damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energ y control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume n t shall be made at the customer?s own risk. polyimide base film is hard and thin. be careful not to injure yourself on the film or to scratch any other parts with the film . try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that ther e is no chance of them injuring themselves. when cutting out the film, try to ensure that the film shavings do not cause accidents. aft er use, treat the leftover film and reel spacers as industrial waste. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause t he device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and du ring inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. the information contained herein is subject to change without notice. 000707 ebe1
T6C13B 2001-02-05 2/11 block diagram
T6C13B 2001-02-05 3/11 pin assignment note: the above diagram shows the pin configuration of the lsi chip, not that of the tape carrier package.
T6C13B 2001-02-05 4/11 pin functions pin name i / o functions level o1 to o240 output output for lcd drive signal v 0 to v5 eio1, eio2 i / o input / output for enable signal dir selects in or out. connect eio (in) of 1st lsi to l. for a cascade connection, connect eio (out) to eio (in) of next lsi. (column mode) input for data signal di1 to di8 input (row mode) di1 to di7 : fix to h or l di8 : 121st enable terminal in dual mode. dir input (direction) input for data flow direction select / dspof input (display off) / dspof = l : display ? off mode, (o1 to o240) remain at the v 5 level. / dspof = h : display ? on mode, (o1 to o240) are operational. (column mode) fix to h or l dual input (row mode) terminal for dual input mode or single input mode select (column mode) display data is latched on falling edges of lp. when eio (in) = l, setting scp lp = h enables the 1st lsi. lp D (row mode) input for shift clock pulse fr input (frame) input for frame signal (column mode) input for shift clock pulse scp input (row mode) fix to h or l test input (test) fix to l or open s / c input input for mode select: h = column mode, l = row mode v dd to v ss v dd D power supply for internal logic (+5.0 v) v ss D power supply for internal logic (0 v) v ss lr D power supply for lcd drive circuit v 5 lr D power supply for lcd drive circuit v 3 / 4 lr D power supply for lcd drive circuit v 2 / 1 lr D power supply for lcd drive circuit v 0 lr D power supply for lcd drive circuit v cc lr D power supply for lcd drive circuit D
T6C13B 2001-02-05 5/11 relation between fr, data input and output level f r data input (di1 to di8) / dspof output level (column mode) output level (row mode) l l h v 3 v 4 l h h v 5 v 0 h l h v 2 v 1 h h h v 0 v 5 D D l v 5 v 5 data input format column mode enable pin input data line and output buffers dir bit mode eio1 eio2 (*1) di1 di2 di3 di4 di5 di6 di7 di8 l o240 o239 o238 o237 o236 o235 o234 o233 h in out f o8 o7 o6 o5 o4 o3 o2 o1 l o1 o2 o3 o4 o5 o6 o7 o8 l 8 ? bit out in f o233 o234 o235 o236 o237 o238 o239 o240 *1: l: last data f: first data row mode data input terminals dual dir data flow eio1 eio2 di8 l l o240 o1 out in D l h o1 o240 in out D h l o120 o1 o240 o121 out in in h h o1 o120 o121 o240 in out in
T6C13B 2001-02-05 6/11 timing diagram (column mode)
T6C13B 2001-02-05 7/11 timing diagram (row mode)
T6C13B 2001-02-05 8/11 absolute maximum ratings (ensure that the following conditions are maintained, v cc v 0 v 2,1 v 3, 4 v 5 v ss ) item symbol pin name rating unit supply voltage 1 v dd v dd ? 0.3 to 6.5 v supply voltage 2 v cc v cc l / r ? 0.3 to 42.0 v supply voltage 3 v 0 , v 2 v 0 l / r , v 2, 1 l / r ? 0.3 to v cc + 0.3 v supply voltage 4 v 3 , v 5 v 3, 4 l / r , v 5 l / r ? 0.3 to 42.0 v input voltage v in (note 2) ? 0.3 to v dd + 0.3 v operating temperature t opr D ? 20 to 75 c storage temperature t stg D ? 40 to 125 c note 2: scp, fr, lp, dir, dual, eio1, eio2, di1 to di8, / dspof, test,s / c electrical characteristics dc characteristics (unless otherwise noted, v ss = 0 v, v dd = 2.7 to 5.5 v, ta = ? 20 to 75c) item symbol test circuit test condition min typ. max unit pin name supply voltage 1 v dd D D 2.7 5.0 5.5 v dd supply voltage 2 v cc D D 14.0 D 40.0 v cc l / r h level v ih D D 0.8 v dd D v dd input voltage l level v il D D 0 D 0.2 v dd scp, fr, lp, dir, dual eio1, eio2, di1 to di8, / dspof, test, s / c h level v oh D i oh = ? 0.5 ma v dd ? 0.5 D vdd output voltage l level v ol D i ol = 0.5 ma 0 D 0.5 v eio1, eio2 h level r oh D v out = v 0 ? 0.5 v (note 3) D 0.4 0.8 r om D v out = v 2 0.5 v (note 3) D 0.4 0.8 m level r om D v out = v 3 0.5 v (note 3) D 0.4 0.8 output resistance l level r ol D v out = v 5 + 0.5 v (note 3) D 0.4 0.8 k ? o1 to o240 i dd D v dd = 5.5 v, v cc = 42 v f fr = 40 hz, f scp = 8.0 mhz input data: every bit inverted v ih = 5.5 v, v il = 0 v (current consumption while the internal data receiver is operating) D D 81.5 ma v dd current consumption (note 4) i dd st / by D current consumption while the internal data receiver is sleeping D D 240 a v dd note 3: v cc = 20 v, 1 / 13 bias
T6C13B 2001-02-05 9/11 ac electrical characteristics (column mode) test conditions (1) (v ss = 0 v, v dd = 2.7 to 4.5 v, v cc = 14 to 42 v, ta = ? 20 to 75c) item symbol test condition min max unit clock cycle t c D 76 D scp pulse width t cwh , t cwl D 26 D data set ? up time t dsu D 26 D data hold time t dhd D 26 D scp rise / fall time t r , t f D D (note 4) lp rise time t lrp D 26 D lp fall time t lfp D 26 D lp pulse width t lw D 26 D scp to lp delay time (scp lp) t sl D 26 D lp to scp delay time (lp scp) t ls D 26 D eio in rise time t eifp D 26 D eio in pulse width t eiw D 26 D scp to eio delay time (scp eio) t se D 0 D eio out delay time t eod (note 5) D 50 ns note 4: t r , t f (t c ? t cwh ? t cwl ) / 2 and t r , t f 50 ns note 5: c l = 10 pf
T6C13B 2001-02-05 10/11 test conditions (2) (v ss = 0 v, v dd = 4.5 to 5.5 v, v cc = 14 to 42 v, ta = ? 20 to 75c) item symbol test condition min max unit clock cycle t c D 37 D scp pulse width t cwh , t cwl D 15 D data set ? up time t dsu D 15 D data hold time t dhd D 15 D scp rise / fall time t r , t f D D (note 6) lp rise time t lrp D 15 D lp fall time t lfp D 15 D lp pulse width t lw D 15 D scp to lp delay time t sl D 15 D lp to scp delay time t ls D 15 D eio in rise time t eifp D 15 D eio in pulse width t eiw D 15 D scp to eio delay time t se D 0 D eio out delay time t eod (note 7) D 25 ns note 6: t r , t f (t c ? t cwh ? t cwl ) / 2 and t r , t f 50 ns note 7: c l = 10 pf
T6C13B 2001-02-05 11/11 ac electrical characteristics (row mode) test conditions (1) (v ss = 0 v, v dd = 2.7 to 4.5 v, v cc = 14 to 42 v, ta = ? 20 to 75c) item symbol test condition min max unit clock cycle t c lp 250 D lp pulse width h t cwh lp 40 D lp pulse width l t cwl lp 170 D scp rise / fall time t r , t f lp, fr, eio1, eio2, di8 D (note 8) data set ? up time t dsu eio1, eio2, di8 100 D data hold time t dhd eio1, eio2, di8 0 D eio out delay time a (note 9) t pda eio1, eio2 40 D eio out delay time b (note 9) t pdb eio1, eio2 0 130 ns test conditions (2) (v ss = 0 v, v dd = 4.5 to 5.5 v, v cc = 14 to 42 v, ta = ? 20 to 75c) item symbol test condition min max unit clock cycle t c lp 150 D lp pulse width h t cwh lp 20 D lp pulse width l t cwl lp 100 D scp rise / fall time t r , t f lp, fr, eio1, eio2, di8 D (note 10) data set ? up time t dsu eio1, eio2, di8 50 D data hold time t dhd eio1, eio2, di8 0 D eio out delay time a (note 11) t pda eio1, eio2 20 D eio out delay time b (note 11) t pdb eio1, eio2 0 100 ns note 8, 10: t r , t f (t c ? t cwh ? t cwl ) / 2 and t r , t f 50 ns note 9, 11: c l = 10 pf note: insert the bypass capacitor (0.1 f) between v dd and v ss and between v cc and v ss to decrease power supply noise. place the bypass capacitor as close to the lsi as possible.

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